#ifndef __BASE_ADDR_H__
#define __BASE_ADDR_H__

#define GX_REG_BASE_PMU              0xA0000000
#define GX_REG_BASE_GPIO0            0xA0001000
#define GX_REG_BASE_PWM0             0xA0002000
#define GX_REG_BASE_RTC              0xA0003000
#define GX_REG_BASE_OSC              0xA0004000
#define GX_REG_BASE_HW_I2C           0xA0005000
#define GX_REG_BASE_PMU_CONFIG       0xA0010000
#define GX_REG_BASE_UART0            0xA0100000
#define GX_REG_BASE_UART0_BRC        0xA0100100
#define GX_REG_BASE_UART1            0xA0200000
#define GX_REG_BASE_UART1_BRC        0xA0200100
#define GX_REG_BASE_MCU_CONFIG       0xA0300000
#define GX_REG_BASE_COUNTER          0xA0400000
#define GX_REG_BASE_I2C0             0xA0500000
#define GX_REG_BASE_I2C1             0xA0600000
#define GX_REG_BASE_WATCHDOG         0xA0700000

#define GX_REG_BASE_AUDIO_IN         0xA0A00000
#define GX_REG_BASE_AHB_AUDIO_OUT    0xA0B80000
#define GX_REG_BASE_SYS_AUDIO_OUT    0xA0B00000

#define GX_REG_BASE_DMA              0xA1000000
#define GX_REG_BASE_XIP_CS           0xA0300090
#define GX_REG_BASE_XIP              0xA2000000
#define GX_REG_BASE_SPI1             0xA3000000
#define GX_REG_BASE_SPI1_CS          0xA030008C
#define GX_REG_BASE_ICACHE           0xB0000000
#define GX_REG_BASE_MMU              0xB0100000

// pmu config
#define PMU_CFG_MEPG_CLD_RST_NORM       (GX_REG_BASE_PMU_CONFIG + 0x00)
#define PMU_CFG_MEPG_CLD_RST_1SET       (GX_REG_BASE_PMU_CONFIG + 0x04)
#define PMU_CFG_MEPG_CLD_RST_1CLR       (GX_REG_BASE_PMU_CONFIG + 0x08)
#define PMU_CFG_MEPG_HOT_RST_NORM       (GX_REG_BASE_PMU_CONFIG + 0x0c)
#define PMU_CFG_MEPG_HOT_RST_1SET       (GX_REG_BASE_PMU_CONFIG + 0x10)
#define PMU_CFG_MEPG_HOT_RST_1CLR       (GX_REG_BASE_PMU_CONFIG + 0x14)
#define PMU_CFG_MEPG_CLK_INHIBIT_NORM   (GX_REG_BASE_PMU_CONFIG + 0x18)
#define PMU_CFG_MEPG_CLK_INHIBIT_1SET   (GX_REG_BASE_PMU_CONFIG + 0x1C)
#define PMU_CFG_MEPG_CLK_INHIBIT_1CLR   (GX_REG_BASE_PMU_CONFIG + 0x20)
#define PMU_CFG_DTO0_CONFIG             (GX_REG_BASE_PMU_CONFIG + 0x24)  // Audio
#define PMU_CFG_POWER_ON_RESET_REG0     (GX_REG_BASE_PMU_CONFIG + 0x2C)
#define PMU_CFG_POWER_ON_RESET_REG1     (GX_REG_BASE_PMU_CONFIG + 0x30)  //For OSC Trim State
#define PMU_CFG_SCPU_CONFIG             (GX_REG_BASE_PMU_CONFIG + 0x34)
#define PMU_CFG_SCPU_STATUS             (GX_REG_BASE_PMU_CONFIG + 0x38)
#define PMU_CFG_XTAL_EN                 (GX_REG_BASE_PMU_CONFIG + 0x4C)
#define PMU_CFG_RST_MCU                 (GX_REG_BASE_PMU_CONFIG + 0x50)
#define PMU_CFG_MCU_OVERRIDE_ADDR       (GX_REG_BASE_PMU_CONFIG + 0x54)
#define PMU_CFG_MCU_OVERRIDE_EN         (GX_REG_BASE_PMU_CONFIG + 0x58)
#define PMU_CFG_RST_PMU                 (GX_REG_BASE_PMU_CONFIG + 0x60)
#define PMU_CFG_FLASH_START             (GX_REG_BASE_PMU_CONFIG + 0x64)
#define PMU_CFG_BOOT_MODE               (GX_REG_BASE_PMU_CONFIG + 0x68)
#define PMU_CFG_CLOCK_DIV_CONFIG0       (GX_REG_BASE_PMU_CONFIG + 0x80)
#define PMU_CFG_CLOCK_DIV_CONFIG1       (GX_REG_BASE_PMU_CONFIG + 0x84)
#define PMU_CFG_CLOCK_DIV_CONFIG2       (GX_REG_BASE_PMU_CONFIG + 0x88)
#define PMU_CFG_SOURCE_SEL0             (GX_REG_BASE_PMU_CONFIG + 0x8C)
#define PMU_CFG_PIN_FUNCTION_SEL0       (GX_REG_BASE_PMU_CONFIG + 0x90)
#define PMU_CFG_PIN_FUNCTION_SEL1       (GX_REG_BASE_PMU_CONFIG + 0x94)
#define PMU_CFG_PIN_FUNCTION_SEL2       (GX_REG_BASE_PMU_CONFIG + 0x98)
#define PMU_CFG_IO_IE_SEL               (GX_REG_BASE_PMU_CONFIG + 0x9c)
#define PMU_CFG_SRAM_GATE_ADDR          (GX_REG_BASE_PMU_CONFIG + 0x100)
#define PMU_CFG_CLK_GATE                (GX_REG_BASE_PMU_CONFIG + 0x104)
#define PMU_CFG_SOURCE_SEL1             (GX_REG_BASE_PMU_CONFIG + 0x108)

// mcu config
#define MCU_CFG_MEPG_CLD_RST_NORM       (GX_REG_BASE_MCU_CONFIG + 0x00)
#define MCU_CFG_MEPG_CLD_RST_1SET       (GX_REG_BASE_MCU_CONFIG + 0x04)
#define MCU_CFG_MEPG_CLD_RST_1CLR       (GX_REG_BASE_MCU_CONFIG + 0x08)
#define MCU_CFG_MEPG_HOT_RST_NORM       (GX_REG_BASE_MCU_CONFIG + 0x0C)
#define MCU_CFG_MEPG_HOT_RST_1SET       (GX_REG_BASE_MCU_CONFIG + 0x10)
#define MCU_CFG_MEPG_HOT_RST_1CLR       (GX_REG_BASE_MCU_CONFIG + 0x14)
#define MCU_CFG_MEPG_CLK_INHIBIT_NORM   (GX_REG_BASE_MCU_CONFIG + 0x18)
#define MCU_CFG_MEPG_CLK_INHIBIT_1SET   (GX_REG_BASE_MCU_CONFIG + 0x1C)
#define MCU_CFG_MEPG_CLK_INHIBIT_1CLR   (GX_REG_BASE_MCU_CONFIG + 0x20)
#define MCU_CFG_DTO0_CONFIG             (GX_REG_BASE_MCU_CONFIG + 0x24)
#define MCU_CFG_DTO1_CONFIG             (GX_REG_BASE_MCU_CONFIG + 0x28)
#define MCU_CFG_CLK_GATE                (GX_REG_BASE_MCU_CONFIG + 0x2C)
#define MCU_CFG_CHIP_ID                 (GX_REG_BASE_MCU_CONFIG + 0x30)
#define MCU_CFG_CLOCK_DIV_CONFIG0       (GX_REG_BASE_MCU_CONFIG + 0x80)
#define MCU_CFG_CLOCK_DIV_CONFIG1       (GX_REG_BASE_MCU_CONFIG + 0x84)
#define MCU_CFG_SOURCE_SEL              (GX_REG_BASE_MCU_CONFIG + 0x88)
#define MCU_CFG_DW_SPI_CONFIG_ADDR      (GX_REG_BASE_MCU_CONFIG + 0x8C)
#define MCU_CFG_DW_SPI_FLASH_ADDR       (GX_REG_BASE_MCU_CONFIG + 0x90)

// Base Address : xip
#define CONFIG_FLASH_XIP_BASE      0x10200000
#define CONFIG_EXTERNAL_FLASH_BASE 0x10300000



#define readl(addr) ({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; })
#define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b))
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))

#endif
